<p class="wordsection1">Create Verilog/System Verilog test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level</p> <ul> <li class="wordsection1">Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump</li> <li class="wordsection1">Run DV regressions & analyze coverage, triage &